1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-layered spacer and a method of manufacturing the same.
2. Description of the Related Art
As the techniques of manufacturing semiconductor devices evolve, integration density improves with a reduction in the size of patterns. In order to increase the integration density of memory devices, i.e., in order to increase the capacity of DRAMs to greater than a gigabit, patterns having a design rule of 0.18 xcexcm or less are needed, along with processes required for the formation of such patterns. In addition, contemporary semiconductor memory devices demand high refresh characteristics. For the improvement of these refresh characteristics, a device having a double-layered spacer has been developed to replace a device having a single-layered spacer made of silicon nitride.
FIGS. 1 through 8 are cross-sectional views for describing the steps of manufacturing a semiconductor device having a conventional double-layered spacer. Referring to FIG. 1, a field area 12 is formed on a semiconductor substrate 10 to define an active area. The active area includes areas 14 where sources and drains will be formed and areas where gate electrodes 18 will be formed. Next, gate electrodes 18 are formed on the semiconductor substrate 10. Each of the gate electrodes 18 include a gate oxide layer 15, a gate conductive layer 16, and a capping dielectric layer 17. A first gate polyoxide layer 19 is grown on the semiconductor substrate 10. In a case where the capping dielectric layer 17 is formed of silicon nitride, the first gate polyoxide layer 19 is not grown on the sidewalls and top of the capping dielectric layer 17. In other words, the first gate polyoxide layer 19 is formed only on the sidewalls of the gate conductive layer 16 and the gate oxide layer 15, and on the semiconductor substrate 10. Impurities are implanted to a low density into the source and drain areas 14 using the gate electrode 18 as an ion implantation mask. The first gate polyoxide layer 19 serves as a buffer layer when implanting impurities.
With reference to FIG. 2, an oxide layer 20 is deposited over the surface of the semiconductor substrate 10 having a step difference due to the presence of the gate electrode patterns 18. A silicon nitride layer is deposited over the surface of the oxide layer 20 having a step difference and is then etched by an anisotropic method, thereby forming external spacers 22 on the sidewalls of the gate electrodes 18. Here, the oxide layer 20 is used as an etching stopper in an etching process of forming the external spacers 22. At the same time, there is a difference in pattern density between different regions of a device, for example in core or periphery region and a cell region in a device. Over etching therefore tends to occur during the etching process for forming external spacers in a core or periphery region having low pattern density. The oxide layer 20 and the first gate polyoxide layer 19 are etched due to this over etching. Thus, the oxide layer 20 does not serve as an etching stopper. As a result, a semiconductor substrate 10, i.e., silicon (Si), is recessed. This recess deteriorates refresh characteristics of a device. Following etching, impurities are implanted to a high density into the source and drain areas 14 to form device sources and drains.
Referring to FIG. 3, the portion of the oxide layer 20 on the semiconductor substrate 10 between the external spacers 22 is removed. The first gate polyoxide layer 19 on the semiconductor substrate 10 between the external spacers 22 is also removed when the oxide layer 20 is etched.
With reference to FIG. 4, a second gate polyoxide layer 23 is grown on the semiconductor substrate 10 between the external spacers 22. The second gate polyoxide layer 23 prevents direct adhesion between the semiconductor substrate 10 and an etching stopper, which will be described below. In other words, the etching stopper, e.g., the silicon nitride layer, does not adhere well to the semiconductor substrate 10. Thus, the second gate polyoxide layer 23 is formed to prevent the silicon nitride layer from separating from the semiconductor substrate 10. The second gate polyoxide layer 23 is formed at a high temperature of about 850xc2x0 C. with the implantation of oxygen. As a result, impurities densely implanted in the source and drain areas 14 are diffused in a lateral direction. Thus, the length of a channel between the source and drain gets shorter. Also, oxygen penetrates into the gate oxide layer 15 through an oxide layer 20a underneath the external spacer 22 when the second gate polyoxide layer 23 is grown. Due to this, both sides of the gate oxide layer 15 get thicker and thus threshold voltage varies. This phenomenon becomes more serious when the integration of semiconductor devices increases and design rules decrease.
An etching stopper 24 is formed over the surface of the semiconductor substrate 10 having a step difference to be used as an etching stopper when a self-aligned contact is etched. The etching stopper 24 is formed of silicon nitride. In the meantime, in a core or periphery area having low pattern density, the second gate polyoxide layer 19 is etched when a photoresist pattern (not shown) is removed in a process of implanting impurity ions. Thus, the etching stopper 24 in the core or periphery area, e.g., the silicon nitride layer, directly adheres to the semiconductor substrate 10. Therefore, the silicon nitride layer may separate from the semiconductor substrate 10 if they are stressed in a subsequent process. This may lead to a phenomenon referred to as bubble defect which results when an inert gas such as argon (Ar), used as an etching gas, penetrates between the semiconductor substrate 10 and the etching stopper 24 when a first interlevel dielectric layer 26 is deposited on the entire surface.
A first interlevel dielectric layer 26 is deposited on the semiconductor substrate 100 on which the etching stopper is formed 24. The first interlevel dielectric layer 26 is planarized by chemical mechanical polishing to ensure a photolithography margin.
Referring to FIG. 5, a photoresist pattern (not shown) is formed using a photolithography, in order to form self-aligned contacts, i.e., areas in which pads will be formed. The photoresist pattern defines the areas in which pads will be formed. The first interlevel dielectric layer 26 is etched using the photoresist pattern as an etching mask until the etching stopper 24 on the source and drain areas 14 is exposed. The etching stopper 24 on the tops and sidewalls of the gate electrodes 18 and the oxide layer 20 on the tops of the gate electrodes 26 are removed when the first interlevel dielectric layer 26 is etched. The capping dielectric layer 17 is also etched to a predetermined thickness. The photoresist pattern is removed using a common method, e.g., an ashing process.
With reference to FIG. 6, the etching stopper 24a and the second gate polyoxide layer 23 remaining on source and drain areas 14 are removed to form pads electrically connected to sources and drains.
Referring to FIG. 7, a polysilicon layer is deposited on the semiconductor substrate 10 and then is then planarized by chemical mechanical polishing, thereby forming pads 28.
With reference to FIG. 8, a second interlevel dielectric layer 30 is formed on the semiconductor substrate 10 on which the pads 28 are formed. Carbon from the second interlevel dielectric layer 30, e.g., PE-TEOS layer, penetrates into the gate oxide layer 15 through an oxide layer 20b formed between the external spacer 22a and the gate electrode 18. As a result, the gate oxide layer 15 is contaminated. A carbon group serves as moveable positive ions in the gate oxide layer 15. Thus, the gate operating voltage Vpp drops and threshold voltage varies, thereby causing serious damage to the device. In order to solve this problem, the second interlevel dielectric layer 30 is deposited and annealed, which shortens the channel. In other words, in a case where the second interlevel dielectric layer 30 is annealed at a high temperature, i.e., at a temperature of about 750xcx9c850xc2x0 C., impurities implanted into the source and drain areas 14 are diffused in a lateral direction. As a result, the length of the channel between a source and drain may be shortened.
The device having the conventional double-layered spacer has the above problems. Among these problems, the representative ones are as follows. The first problem is that an oxide layer is over-etched when an external spacer is formed in a core or periphery area having low pattern density. As a result, the oxide layer does not serve as an etching stopper. Thus, the semiconductor substrate, i.e., silicon (Si), becomes recessed, which deteriorates refresh characteristics of the resulting device. Second, a second gate polyoxide layer is formed to supplement low adhesion between an etching stopper, e.g., a silicon nitride layer, and the semiconductor substrate. The second gate polyoxide layer is formed at a high temperature of about 850xc2x0 C., which diffuses impurities densely implanted in the source and drain areas in a lateral direction. Thus, the length of a channel between the source and drain is shortened. Also, oxygen penetrates into a gate oxide layer through an oxide layer underneath the external spacer when the second gate polyoxide layer is grown. As a result, both sides of the gate oxide layer are thickened and threshold voltage varies. Third, the second gate polyoxide layer is etched when the photoresist pattern is removed in a process of implanting impurity ions into a core or periphery area having low pattern density. Thus, an etching stopper in the core or periphery area, e.g., a silicon nitride layer, directly contacts the semiconductor substrate. The silicon nitride layer separates from the semiconductor substrate if they are stressed in a subsequent process. Fourth, Carbon from the second interlevel dielectric layer, e.g., PE-TEOS layer, penetrates into the gate oxide layer through an oxide layer formed between the external spacer and the gate electrode. Due to this, the gate oxide layer is contaminated. A carbon group serves as moveable positive ions in the gate oxide layer. Thus, the gate operating voltage Vpp drops and threshold voltage varies, thereby causing serious damage to a device. In order to solve this problem, the second interlevel dielectric layer is deposited and annealed, which shortens the channel. In other words, in a case where the second interlevel dielectric layer is annealed at a high temperature, impurities implanted in the source and drain areas are diffused in a lateral direction. As a result, the length of a channel between the source and drain may be shortened.
To solve the above problems, it is an object of the present invention to provide a semiconductor substrate having a double-layered spacer which can reduce a short channel effect by reducing a heat budge process, reduce changes in threshold voltage by preventing the penetration of carbon or oxygen into a gate oxide layer, and improve refresh characteristics.
It is another object of the present invention to provide a method of manufacturing a semiconductor substrate having a double-layered spacer which can reduce a short channel effect by reducing a heat budge process, reduce changes in threshold voltage by preventing the penetration of carbon or oxygen into a gate oxide layer, and improve refresh characteristics.
Accordingly, to achieve the above first object, there is provided a semiconductor substrate having a multi-layered spacer. The semiconductor substrate includes: a plurality of gate electrodes each including a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor substrate; a gate polyoxide layer formed on sidewalls of the gate oxide layer and the gate conductive layer and being in contact with a predetermined portion of the semiconductor substrate; a silicon nitride layer being in contact with both sidewalls of the capping dielectric layer and the gate polyoxide layer; an oxide layer being in contact with the silicon nitride layer; and an external spacer being in contact with the oxide layer.
The semiconductor substrate further includes a pad formed in a region between adjacent gate electrodes having the multi-layered spacer and being contact with the semiconductor substrate and an interlevel dielectric layer formed on the pad and each gate electrode having the multi-layered spacer.
Preferably, the gate polyoxide layer prevents the silicon nitride layer from separating from the semiconductor substrate and has a thickness of about 50xcx9c100. The gate polyoxide layer is an oxide layer formed at a temperature of about 800xcx9c900xc2x0 C. with the injection of oxygen.
Preferably, the silicon nitride layer has a thickness of about 100xcx9c500 xc3x85.
The oxide layer is an oxide layer formed at a temperature of about 600xcx9c800xc2x0 C. using SiCl4 and O2. Preferably, the oxide layer is a middle temperature oxide layer or a high temperature oxide layer having a dielectric constant of 3.9, and has a thickness of about 100xcx9c500 xc3x85.
Preferably, the external spacer is formed of silicon nitride or silicon oxynitride.
To achieve the second object, there is provided a method of manufacturing a semiconductor device having a multi-layered spacer. In the method, a plurality of gate electrodes each having a gate oxide layer, a gate conductive layer, and a capping dielectric layer are formed on a semiconductor substrate. A polyoxide layer is formed on both sidewalls of the gate oxide layer and the gate conductive layer and on the semiconductor substrate. A silicon nitride layer is formed over the surface of the semiconductor substrate having a step difference. An oxide layer is deposited over the surface of the silicon nitride layer having a step difference. An external spacer is formed by depositing a dielectric layer for a spacer over the surface of the oxide layer having a step difference and then etching the dielectric layer by an anisotropic method. A first interlevel dielectric layer is formed on the entire surface of the semiconductor substrate. A photoresist pattern is formed to define an area in which a pad will be formed, for example by using photolithography. The first interlevel dielectric layer is etched using the photoresist pattern as an etching mask. The photoresist pattern is removed. The silicon nitride layer and the gate polyoxide layer formed on the semiconductor substrate between the gate electrodes are removed.
Impurity ions may be lightly implanted into the semiconductor substrate between the formation of the gate polyoxide layer on a predetermined portion of the sidewalls of each gate electrode and on the semiconductor substrate and the formation of the silicon nitride layer over the surface of the semiconductor substrate having a step difference therewith.
Impurity ions may be heavily implanted into the semiconductor substrate between the formation of the external spacer by depositing a dielectric layer for a spacer over the surface of the oxide layer having a step difference and then etching the dielectric layer by an anisotropic method and the formation of the first interlevel dielectric layer on the entire surface of the semiconductor substrate.
After removing the silicon nitride layer and the gate polyoxide layer formed on the semiconductor substrate between the gate electrodes, a pad may be formed by depositing a conductive layer on the semiconductor substrate and then planarizing the resultant structure by chemical mechanical polishing and a second interlevel dielectric layer may be formed on the semiconductor substrate on which the pad is formed.
Preferably, the gate polyoxide layer is formed at a temperature of about 800xcx9c900xc2x0 C. with the injection of oxygen. The gate polyoxide layer prevents the silicon nitride layer from coming off of the semiconductor substrate and has a thickness of about 50xcx9c100 xc3x85.
Preferably, the silicon nitride layer is formed to a thickness of about 100xcx9c500 xc3x85.
Preferably, the oxide layer is formed at a temperature of about 600xcx9c800xc2x0 C. using SiCl4 and O2. It is preferable that the oxide layer is a middle temperature oxide layer or a high temperature oxide layer having a dielectric constant of 3.9, and has a thickness of about 100xcx9c500 xc3x85.
Preferably, the dielectric layer for the spacer is formed of oxide or silicon nitride.
The dielectric layer for the spacer is etched by an anisotropic method until the oxide layer is exposed.
Preferably, when etching the dielectric layer for the spacer, a C-F-based gas having an etch selectivity ratio of greater than 10 of the dielectric layer for the spacer to the oxide layer is used, oxygen is used as a reaction gas, and an inert gas is used as an atmosphere.
Preferably, the dielectric layer for the spacer is etched by an anisotropic method at a pressure of about 20xcx9c100 mT, at a temperature of about 20xcx9c60xc2x0 C., and at a source power of 400xcx9c800 W.
Preferably, the first interlevel dielectric layer is a HDP layer, a BPSG layer, a USG layer, a PE-TEOS layer or an SOG layer.
The first interlevel dielectric layer is etched until the silicon nitride layer on the semiconductor substrate between the gate electrodes is exposed.
The first interlevel dielectric layer is etched using a C-F-based gas having an etch selectivity ratio of greater than 10 of the first interlevel dielectric layer to the silicon nitride layer.